1. Field of the Invention
This invention relates to a logic circuit used in a standard IC of CMOS logic level, and more particularly to a logic circuit attaining high speed operation.
2. Description of the related art including information disclosed under .sctn..sctn.1.97-1.99
In general, a logic circuit used in a standard IC of CMOS logic level includes a CMOS inverter circuit, as shown in FIG. 1, for example. The CMOS inverter circuit shown in this Figure includes a P channel MOSFET 12 and an N channel MOSFET 13 which are serially connected between power source potential (Vcc) terminal 11 and ground terminal Vss. Input terminal T1 is connected to the gates of MOSFETs 12 and 13 and output terminal T2 is connected to the connection point therebetween. The input threshold voltage of the logic circuit of the above CMOS structure is set at an intermediate level between power source potential Vcc and ground potential Vss, and the amplitude of an output signal is large. Since no through current flows from power source potential Vcc terminal 11 to ground terminal Vss at times other than the switching transition time, this circuit therefore not only has a high resistance to noise but also a low power consumption.
FIG. 2 shows characteristics between an output voltage and an output current of the CMOS inverter circuit of FIG. 1 when an output signal of "L" level is generated. As is clearly seen from the characteristics, the CMOS inverter circuit will have output resistor R.sub.ON of constant resistance in the range of low output voltage.
Since an input capacitor of an external circuit and capacitive load C.sub.L such as a wiring layer having a parasitic capacitance may be connected to output terminal T2, an equivalent circuit including the load of the inverter circuit of FIG. 1 may be obtained as shown in FIG. 3. In FIG. 3, resistor R.sub.ON is an ON resistance of P channel MOSFET 12 and N channel MOSFET 13 and inductor L corresponds to the sum of the inductance of an internal wiring layer and the inductance of a wiring layer to the external circuit. Further, capacitor C.sub.L represents an input capacitance.
In the FIG. 3 circuit, a potential difference across load C.sub.L or output voltage V is monotonically attenuated at the falling time of an output signal or at the switching time of movable contact ST1 of switch SW from fixed contact ST2 to fixed contact ST3 if resistor R.sub.ON has a sufficiently high resistance. However, in a CMOS inverter circuit which is required to have a high speed operation, it is necessary to set resistor R.sub.ON sufficiently low. For this reason, output voltage V is attenuated in the cosine waveform as shown in FIG. 4, causing a ringing oscillation.
In a case where ON-resistor R.sub.ON is set to have a low resistance, a series resonant circuit of inductor L and capacitor C.sub.L will not receive a sufficiently large damping effect, causing the potential difference across resistor R.sub.ON to be set at a low level. However, in this case, the potential differences across inductor L and capacitor C.sub.L are generated in a resonant waveform, thus causing the ringing oscillation. Further, when the resistance of ON-resistor R.sub.ON is set at a low level, the ringing also occurs at the time of rising of an output signal.
When the ON-resistances of MOSFETs 12 and 13 are set at a low level to enhance the operation speed, a large current or rush current flows from power source potential Vcc terminal 11 to ground terminal Vss at the switching transition time at which MOSFETs 12 and 13 are set ON at the same time. Thus, power source potential Vcc is instantaneously lowered, generating noise and the power consumption is increased.